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SALARY: Up to €95'000

COMPANY: Our client develops ultra-low power processors that mimic the brain’s mechanisms for processing fast data streams from sensors, enabling complex sensor analytics functionalities. Additionally, these processors allow data to be processed faster and with up to 99.75% less energy than with traditional processors.

JOB RESPONSIBILITIES:

• Designing and architecting digital IP and subsystems. Making sure the IP under test gets fully verified by the verification engineer.
• Designing and architecting the So C level integrating all IP and subsystems. Aiding in verifying the So C functionality with top-level tests. Deep understanding of the SW-HW system.
• Assisting and/or performing all front-end design tasks: design, verification, DFT, synthesis, STA and formal equivalence checking.

REQUIREMENTS:

• At least 10 years of experience in ASIC Design.
• Demonstrate ability to design from scratch complex digital modules, preferably in the area of HW accelerators, Computer Vision, DSP or Neural Networks. Power aware design and understanding of power domains.
• Experience in architecting complex SOC subsystems or even entire SOCs.
• Design or integration of RISC/DSP processors and their ecosystem.
• Strong verification skills with impeccable reuse and best practices.
• Experience with various fast & slow communication protocols (SPI, I2C, UART, …) and on-chip bus protocols (AMBA, OBI, …).
• Test methodologies (using JTAG, scan, memory BIST).
• EDA tool flows and scripting (eg: in Python).
• (Embedded) C and/or C++ and/or System C.
• Synthesis, timing analysis and timing closure.
• Chip bring-up, silicon and system debug.

INTERVIEW PROCESS: Meeting with HR -> Technical interview with VP of Engineering -> Meet the team -> Offer